Semiconductor device and manufacturing method of the same

ABSTRACT

A trench is formed so as to reach a p − -type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.

CROSS-REFERENCE TO RELATED APPLICATION

The disclosure of Japanese patent application No. 2006-295435 filed onOct. 31, 2006 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and itsmanufacturing technology, and particularly to a semiconductor device inwhich a trench gate type MISFET (Metal Insulator Semiconductor FieldEffect Transistor) having a p channel is provided with an overheatcutoff circuit, and a technology effective if applied to itsmanufacture.

A power MISFET with an overheat cutoff circuit built therein has beendisclosed in Japanese Unexamined Patent Publication No. Sho63(1988)-229758 (Patent Document 1). According to a technology describedin the patent document 1, a gate resistor is provided between a gateelectrode of the power MISFET and an external gate terminal (gate pad).Further, a protection circuit MISFET is provided between the gateelectrode of the power MISFET and a source electrode thereof. When thepower MISFET is brought to an overheated state, the protection circuitMISFET is turned on to allow current to flow through the gate resistor.Thus, the voltage applied to the gate electrode of the power MISFET isreduced to turn off the power MISFET, thereby preventing devicebreakdown due to overheating.

A technology for enhancing avalanche capability or breakdown toleranceof a trench gate type power MISFET having an n channel has beendisclosed in Japanese Unexamined Patent Publication No. 2005-57049(Patent Document 2). Described specifically, a p⁺-type semiconductorregion is formed at the bottom of a contact trench or groove of thetrench gate type power MISFET. A p-type semiconductor region, whichcontacts the p⁺-type semiconductor region and an n⁻-type monocrystallinesilicon layer and is lower in impurity concentration than the p⁺-typesemiconductor region, is formed below the p⁺-type semiconductor region.Further, an n-type semiconductor region, which contacts the p-typesemiconductor region and is higher in impurity concentration than then⁻-type monocrystalline silicon layer, is formed in the n⁻-typemonocrystalline silicon layer below the p-type semiconductor region.

SUMMARY OF THE INVENTION

A high power-purpose transistor capable of treating a power of a fewwatts or higher is called power transistor. Ones having variousstructures exist. As to power MISFETs of all, there are known onescalled so-called vertical and lateral structures depending upon thedirection of current flowing through a channel. Further, there are knownstructures called a trench gate type power MISFET and a planar typepower MISFET according to the structures of their gate electrodes. As tosuch power MISFETs, a large number of the power MISFETs are used withbeing connected in parallel to obtain high power.

The power MISFETs are classified into a p channel power MISFET and an nchannel power MISFET depending on the type of carriers flowing throughtheir channels. In the p channel power MISFET, positive holes are usedas a majority carrier. In the n channel power MISFET, electrons are usedas a majority carrier.

In general, a p channel trench gate type power MISFET has the featurethat it is hard to cause avalanche breakdown as compared with an nchannel trench gate type power MISFET. This is because the currentamplification gain (hFE) of a pnp bipolar transistor parasiticallyexisting in the p channel trench gate type power MISFET is much smallerthan that of an npn bipolar transistor parasitically existing in the nchannel trench gate type power MISFET. This is also because the mobilityof positive holes corresponding to carriers of the p channel trench gatetype power MISFET is smaller by about ¼ than the mobility of electronscorresponding to carriers of the n channel trench gate type powerMISFET. Accordingly, it can be said that the shortage of avalanchecapability becomes almost insignificant in the single p channel trenchgate type power MISFET.

Here, there is known a power MISFET with an overheat cutoff circuitbuilt therein in order to prevent breakdown of the power MISFET andenhance its reliability. As described in the patent document 1, forexample, there is known, as the overheat cutoff circuit, one providedwith a gate resistor between a gate electrode of a power MISFET and agate terminal (gate pad) and provided with a protection circuit MISFETbetween the gate electrode of the power MISFET and a source electrodethereof. According to the overheat cutoff circuit, when the power MISFETis brought to an overheated state, the protection circuit MISFET isturned on to allow current to flow through the gate resistor. Thus, thevoltage applied to the gate electrode of the power MISFET is lowered toturn off the power MISFET, thereby preventing device breakdown due tooverheating.

As the power MISFET with the overheat cutoff circuit built therein,there is known one wherein an overheat cutoff circuit is incorporated ina p channel trench gate type power MISFET. The p channel trench gatetype power MISFET with the overheat cutoff circuit built therein hascaused a problem that avalanche capability (L load tolerance orcapability) is reduced with respect to a target value. It is understoodthat since a single p channel trench gate type power MISFET presents noproblem in terms of avalanche capability, and a p channel planar typepower MISFET with an overheat cutoff circuit of the same circuitconfiguration built therein has sufficiently high avalanche capability,this problem is a problem peculiar to the p channel trench gate typepower MISFET with the overheat cutoff circuit built therein.

An object of the present invention is to provide a technique capable ofenhancing reliability in a semiconductor device in which a trench gatetype MISFET having a p channel is provided with an overheat cutoffcircuit.

The above, other objects and novel features of the present inventionwill become apparent from the description of the present specificationand the accompanying drawings.

Summaries of representative ones of the inventions disclosed in thepresent application will be explained in brief as follows:

A semiconductor device according to the present invention relates to asemiconductor device including a trench gate type MISFET having a p-typechannel and a resistive element provided between a gate pad and a gateelectrode of the trench gate type MISFET. The semiconductor deviceincludes (a) a semiconductor substrate, (b) a p-type semiconductorregion formed over the semiconductor substrate, (c) an n-type channelforming area formed over the p-type semiconductor region, and (d) ap-type source region formed over the n-type channel forming area.Further, the semiconductor device includes (e) a trench which extendsfrom an upper surface of the p-type source region to the p-typesemiconductor region, (f) a gate insulating film formed over an innerwall of the trench, and (g) a gate electrode formed over the gateinsulating film and formed so as to bury the trench. The semiconductordevice includes (h) a first n-type semiconductor region formed withinthe n-type channel forming area and having an impurity introducedtherein in a concentration higher than the n-type channel forming area,and (i) a second n-type semiconductor region formed in an area deeperthan the first n-type semiconductor region and shallower than the bottomof the trench, which has an impurity introduced therein in aconcentration lower than the first n-type semiconductor region and animpurity introduced therein in a concentration higher than the n-typechannel forming area.

A method for manufacturing a semiconductor device according to thepresent invention relates to a method of manufacturing a semiconductordevice including a trench gate type MISFET having a p-type channel and aresistive element provided between a gate pad and a gate electrode ofthe trench gate type MISFET. The method includes the steps of (a)forming a p-type semiconductor region over a semiconductor substrate,(b) forming a trench in the p-type semiconductor region, (c) forming agate insulating film over an inner wall of the trench, and (d) forming agate electrode so as to bury the trench. Further, the method includesthe steps of (e) forming an n-type channel forming area in an areashallower than the trench of the p-type semiconductor region, (f)forming a p-type source region in a surface region shallower than thebottom of the n-type channel forming area, and (g) forming a firstn-type semiconductor region in the n-type channel forming area. Themethod includes the step of (h) forming a second n-type semiconductorregion in an area deeper than the first n-type semiconductor region andshallower than the bottom of the trench. An impurity concentration ofthe second n-type semiconductor region is lower than that of the firstn-type and higher than that of the n-type channel forming area.

Advantageous effects obtained by a representative one of the inventionsdisclosed in the present application will be explained in brief asfollows:

A high-concentration n-type semiconductor region of the same conductiontype as a channel forming area is formed directly below each bodycontact region. Thus, a point brought to avalanche breakdown with a pnjunction existing in the boundary between the channel forming area and adrain region can be formed to a position spaced away from a sidewall ofa trench gate electrode. Therefore, it is possible to suppress theflowing of an electron current produced upon the avalanche breakdownthrough the sidewall of the trench gate electrode and to reduceelectrons injected into the gate electrode. As a result, it is possibleto prevent a voltage drop developed across a resistive element connectedin series with the gate electrode and to prevent a phenomenon that a pchannel trench gate type power MISFET is turned on so that its deviceoperation exceeds an area of safe operation, whereby the p channeltrench gate type power MISFET is brought to thermal breakdown.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit block diagram showing a p channel trench gate typepower MISFET with an overheat cutoff circuit built therein in a firstembodiment of the present invention;

FIG. 2 is a circuit block diagram showing where an n channel powerMISFET is used as a high side switch for lighting a lamp;

FIG. 3 is a circuit block diagram showing where a p channel power MISFETis used as a high side switch for lighting a lamp;

FIG. 4 is a diagram illustrating a circuit for measuring avalanchecapability of a p channel trench gate type power MISFET;

FIG. 5 is a typical diagram showing a p channel trench gate type powerMISFET;

FIG. 6 is a diagram illustrating a circuit for measuring avalanchecapability of a p channel trench gate type power MISFET with an overheatcutoff circuit built therein;

FIG. 7 is a diagram showing switching waveforms at the time that theavalanche capability is measured with a circuit configuration shown inFIG. 6;

FIG. 8 is a graph showing relationships between a breakdown voltagebetween a source region and a drain region and a drain current densityand between the breakdown voltage and a gate current density in a pchannel planar type power MISFET;

FIG. 9 is a graph showing relationships between a breakdown voltagebetween a source region and a drain region and a drain current densityand between the breakdown voltage and a gate current density in a pchannel trench gate type power MISFET;

FIG. 10 is a sectional view illustrating a sectional structure of a pchannel planar type power MISFET;

FIG. 11 is a sectional view depicting a sectional structure of a pchannel trench gate type power MISFET;

FIG. 12 is a plan view typically showing a semiconductor chip in which asemiconductor device according to the first embodiment is formed;

FIG. 13 is a sectional view illustrating a sectional structure of a pchannel trench gate type power MISFET;

FIG. 14 is a sectional view showing avalanche breakdown points of the pchannel trench gate type power MISFET according to the first embodiment;

FIG. 15 is a graph illustrating a relationship between the rate of thedepth of an n-type semiconductor region to the depth of a channelforming area and an avalanche peak current;

FIG. 16 is a graph showing a relationship between the ratio of the depthof an n-type semiconductor region to the depth of a channel forming areaand a breakdown voltage;

FIG. 17 is a sectional view illustrating a process of manufacturing thesemiconductor device according to the first embodiment;

FIG. 18 is a sectional view following FIG. 17, showing the semiconductordevice manufacturing process;

FIG. 19 is a sectional view following FIG. 18, showing the semiconductordevice manufacturing process;

FIG. 20 is a sectional view following FIG. 19, showing the semiconductordevice manufacturing process;

FIG. 21 is a sectional view following FIG. 20, showing the semiconductordevice manufacturing process;

FIG. 22 is a sectional view following FIG. 21, showing the semiconductordevice manufacturing process;

FIG. 23 is a sectional view following FIG. 22, showing the semiconductordevice manufacturing process;

FIG. 24 is a sectional view following FIG. 23, showing the semiconductordevice manufacturing process;

FIG. 25 is a sectional view following FIG. 24, showing the semiconductordevice manufacturing process;

FIG. 26 is a sectional view following FIG. 25, showing the semiconductordevice manufacturing process;

FIG. 27 is a sectional view following FIG. 26, showing the semiconductordevice manufacturing process;

FIG. 28 is a sectional view following FIG. 27, showing the semiconductordevice manufacturing process;

FIG. 29 is a sectional view showing examples for forming resist patternsdifferent from FIG. 28;

FIG. 30 is a sectional view following FIG. 28, showing the semiconductordevice manufacturing process;

FIG. 31 is a sectional view following FIG. 30, showing the semiconductordevice manufacturing process;

FIG. 32 is a sectional view following FIG. 31, showing the semiconductordevice manufacturing process;

FIG. 33 is a sectional view showing a process of manufacturing asemiconductor device according to a second embodiment;

FIG. 34 is a sectional view following FIG. 33, showing the semiconductordevice manufacturing process; and

FIG. 35 is a sectional view following FIG. 34, showing the semiconductordevice manufacturing process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be described by being divided into a plurality ofsections or embodiments whenever circumstances require it forconvenience in the following embodiments. However, unless otherwisespecified in particular, they are not irrelevant to one another. Onethereof has to do with modifications, details and supplementaryexplanations of some or all of the other.

When reference is made to the number of elements or the like (includingthe number of pieces, numerical values, quantity, range, etc.) in thefollowing embodiments, the number thereof is not limited to a specificnumber and may be greater than or less than or equal to the specificnumber unless otherwise specified in particular and definitely limitedto the specific number in principle.

It is further needless to say that components or constituent elements(including element or factor steps, etc.) employed in the followingembodiments are not always essential unless otherwise specified inparticular and considered to be definitely essential in principle.

Similarly, when reference is made to the shapes, positional relationsand the like of the components or the like in the following embodiments,they will include ones substantially analogous or similar to theirshapes or the like unless otherwise specified in particular andconsidered not to be definitely so in principle, etc. This is similarlyapplied even to the above-described numerical values and range.

Throughout all drawings for describing the embodiments, identicalmembers are respectively identified by the same reference numerals inprinciple and their repetitive explanations will therefore be omitted.Incidentally, some hatching might be provided to make it easy to readthe drawings even in the case of plan views.

First Preferred Embodiment

A semiconductor device according to a first embodiment will be explainedwith reference to the accompanying drawings. The semiconductor deviceaccording to the first embodiment is a p channel trench gate type powerMISFET with an overheat cutoff circuit built therein. The trench gatetype power MISFET is of a power MISFET of a structure in which a gateelectrode is formed so as to be embedded in its corresponding trench(groove) formed in the direction of the thickness of a semiconductorsubstrate. A p channel indicates that a major carrier of the powerMISFET is a positive hole.

FIG. 1 is a circuit block diagram showing a p channel trench gate typepower MISFET1 with an overheat cutoff circuit built therein. In FIG. 1,the overheat cutoff circuit 2 is connected to the p channel trench gatetype power MISFET 1. The overheat cutoff circuit 2 is of a circuit forforcibly turning off the p channel trench gate type power MISFET1 toprotect it when the p channel trench gate type power MISFET1 is broughtto an overheated state.

The overheat cutoff circuit 2 has a gate cutoff resistor 3, atemperature detection circuit 4, a latch circuit 5 and a protectiveMISFET 6. The gate cutoff resistor 3 is provided in series between agate electrode of the p channel trench gate type power MISFET1 and agate pad. The protective MISFET 6 is formed between the gate cutoffresistor 3 and a source pad to which a source region of the p channeltrench gate type power MISFET 1 is connected. Further, the temperaturedetection circuit 4 and the latch circuit 5 are connected between thegate pad and the source pad. The latch circuit 5 is connected to thegate electrode of the protective MISFET 6. As the temperature detectioncircuit 4, for example, one using a diode can be used. That is, sincethe diode changes in resistance with a change in temperature, thetemperature can be detected by utilizing the change in resistance withits temperature change.

Next, the operation of the overheat cutoff circuit 2 will be explained.At normal times, a gate voltage is inputted from the gate pad shown inFIG. 1 to the gate electrode of the p channel trench gate type powerMISFET 1. In doing so, the p channel trench gate type power MISFET1 isturned on to allow current to flow between the drain pad and the sourcepad. When, at this time, a load (not shown) connected to the p channeltrench gate type power MISFET1 is short-circuited on a system due to 14some reasons, for example, a power supply voltage is applied to the pchannel trench gate type power MISFET 1 while the gate electrode remainsin a turned-on state, so that the p channel trench gate type powerMISFET1 is brought into a state in which a large current (saturatedcurrent of MISFET) flows. Therefore, the p channel trench gate typepower MISFET1 is brought into an overheated state. Since the p channeltrench gate type power MISFET 1 is brought to destruction when itsoverheated state continues, the overheat cutoff circuit 2 operates.

First, the temperature detection circuit 4 detects the temperature ofthe p channel trench gate type power MISFET 1. When the temperature ofthe p channel trench gate type power MISFET1 reaches a predeterminedtemperature or higher, the temperature detection circuit 4 turns on theprotective MISFET 6 via the latch circuit 5. In doing so, a cutoffcurrent flows between the gate pad and the source pad through theprotective MISFET 6. Since the cutoff current flows through even thegate cutoff resistor 3, a voltage drop is developed due to the flow ofthe cutoff current through the gate cutoff resistor 3. In doing so, thevoltage applied to the gate electrode of the p channel trench gate typepower MISFET 1 becomes a threshold voltage or less, so that the pchannel trench gate type power MISFET1 is turned off. Thus, when the pchannel trench gate type power MISFET 1 is overheated, the p channeltrench gate type power MISFET1 is forcibly turned off by operating theoverheat cutoff circuit 2. Accordingly, the breakdown of the p channeltrench gate type power MISFET1 due to the overheat can be prevented.According to the p channel trench gate type power MISFET1 with theoverheat cutoff circuit 2 built therein from the above, reliability canbe improved.

In FIG. 1, the overheat cutoff circuit 2 is explained by citing oneusing the gate cutoff resistor. The overheat cutoff circuit 2 that makesuse of the gate cutoff resistor 3 has the gate cutoff resistor 3 and theprotective MISFET 6 to turn off the p channel trench gate type powerMISFET 1. Turing off the p channel trench gate type power MISFET 1 isrealized by turning on the protective MISFET 6 to thereby allow the gatecutoff resistor 3 to cause a voltage drop and setting the voltageapplied to the gate electrode of the p channel trench gate type powerMISFET1 to its threshold voltage or less. The voltage applied to thegate electrode of the p channel trench gate type power MISFET1 isdetermined by the ratio of the gate cutoff resistor 3 and the onresistance of the protective MISFET 6. In this case, it is necessarythat the on resistance of the protective MISFET 6 is sufficientlyreduced as compared with the gate cutoff resistor 3 to set the voltageapplied to the gate electrode of the p channel trench gate type powerMISFET1 to the threshold voltage or less (1V or less in general).

It is also necessary to set the value of the cutoff current to currentdrive capacity or less of an external drive circuit. This is becausewhen the current greater than the current drive capacity is pulled in asthe cutoff current, the output of the external drive circuit is reduced,so that the normal voltage cannot be outputted. The value of the cutoffcurrent is substantially determined by the voltage (voltage applied tothe gate pad) applied by the external drive circuit and the gate cutoffresistor 3.

Since the temperature detection circuit 4 and the like that constitutethe overheat cutoff circuit 2 are supplied with the power supply fromthe gate pad as shown in FIG. 1, there is a fear that the overheatcutoff circuit 2 fails to operate in the normal manner due to externalnoise with variations in power-supply voltage or the like. For example,there is a possibility that such an oscillation phenomenon that cutoffand its release are repeated takes place, so that a normal cutting-offfunction will not be obtained. To avoid it, the gate cutoff resistor 3formed in the overheat cutoff circuit 2 normally often makes use of aresistance greater than or equal to 5 kΩ. That is, it is necessary touse the gate cutoff resistor 3 of 5 kΩ or more for the purpose ofpreventing the oscillation phenomenon at the overheat cutoff circuit 2.On the other hand, when the resistance value of the gate cutoff resistor3 is excessively increased, the switching speed of the p channel trenchgate type power MISFET1 becomes slow. Therefore, there is provided anupper limit to the resistance value of the gate cutoff resistor 3. Fromthis point of view, a resistance ranging from 5 kΩ to 20 kΩ is oftenused as for the gate cutoff resistor 3 employed in the overheat cutoffcircuit 2.

Meanwhile, an n channel power MISFET whose carriers are electrons, and ap channel power MISFET whose carriers are positive holes are known aspower MISFETs. Both of these power MISFETs might be used as switchingelements, for example. Here, such a configuration that a power MISFETused as a switching element is disposed on the source potential siderather than the load side is called “high side switch”, whereas such aconfiguration that a power MISFET used as a switching element isdisposed on the ground potential side rather than the load side iscalled “low side switch”. The n channel power MISFET and the p channelpower MISFET are used as the high side switches, for example. However,the constitution of the high side switch by the p channel power MISFETbrings about an advantage in that a drive circuit can be simplified ascompared with the configuration of the high side switch by the n channelpower MISFET. This point will be explained.

FIG. 2 is a circuit block diagram showing a case in which an n channelpower MISFET is used as a high side switch for lighting a lamp (load),for example. As shown in FIG. 2, an n channel power MISFET 8 is providedon the source potential side of a lamp 7. A step-up circuit 9 forcontrolling switching of the n channel power MISFET 8 is connected to agate electrode of the n channel power MISFET 8. Lighting/lighting-out ofthe lamp 7 can be performed by controlling on/off of the n channel powerMISFET 8 by means of the step-up circuit 9.

When the n channel power MISFET 8 is used as the high side switch, it isnecessary to apply a drive voltage (V_(G) =V_(in) (input voltage)+V_(GS)(threshold voltage)) higher than the input voltage to the gateelectrode. Therefore, the step-up circuit 9 becomes necessary as shownin FIG. 2, and a drive circuit for driving the n channel power MISFET 8becomes complex.

On the other hand, a circuit block diagram at the that the p channelpower MISFET is used as a high side switch for lighting a lamp is shownin FIG. 3. As shown in FIG. 3, a p channel power MISFET 10 is providedon the source potential side of a lamp 7. A step-up circuit is notprovided at the gate electrode of the p channel power MISFET 10. Thatis, since the p channel power MISFET 10 can be driven by a drive voltage(V_(G)=V_(in) (input voltage) −V_(GS) (threshold voltage)) lower than aninput voltage when the p channel power MISFET 10 is used as the highside switch, a drive circuit for driving the p channel power MISFET 10can be simplified. Thus, when the p channel power MISFET 10 is used asthe high side switch as compared with the case in which the n channelpower MISFET 8 is used as the high side switch, it can be said that itcan realize a small-sized and simple system and is excellent in generalversatility.

Even in the power MISFETs each having the overheat cutoff circuit builttherein, there are known a product using the p channel power MISFET anda product using the n channel power MISFET. For the above-describedreason, the p channel power MISFET with the overheat cutoff circuitbuilt therein has superiority in terms of general versatility and isexpected to meet requests from a wide range of customers.

It has heretofore been a common practice to use a planar type powerMISFET as the power MISFET having the overheat cutoff circuit builttherein. The planar type power MISFET has a structure in which a gateelectrode is formed on a main surface of a semiconductor substrate.Since, however, it is difficult to reduce a cell size in the planar typepower MISFET, there was a limit to a reduction in on resistance. Thus,it has been discussed that a trench type power MISFET is adopted insteadof the conventional planar type power MISFET to shrink each cell,thereby reducing the on resistance as compared with the planar typepower MISFET.

Next, a description will be made of the avalanche capability of the pchannel trench gate type power MISFET. The avalanche capabilityindicates an index of each element being not destroyed by avalanchebreakdown. FIG. 4 is a diagram illustrating a circuit for measuring theavalanche capability of a p channel trench gate type power MISFET 1. Asshown in FIG. 4, an inductor 11 and a source or power supply 12 areconnected to a drain pad of the p channel trench gate type power MISFET1. A source pad for the p channel trench gate type power MISFET1 and aterminal located on the side of being unconnected to the inductor 11 forthe power supply 12 are grounded. A pulse generator is connected to agate pad of the p channel trench gate type power MISFET. A descriptionwill be made of such a mechanism that the p channel trench gate typepower MISFET will cause avalanche breakdown in the circuit configured inthis way.

FIG. 5 is a typical diagram showing a p channel trench gate type powerMISFET. In FIG. 5, a p-type semiconductor substrate (p⁻-type epitaxiallayer) is formed as a drain region. A channel forming area (n⁻-typesemiconductor region) corresponding to a body area is formed on thesemiconductor substrate. A source region (p⁺-type semiconductor region)is formed at the upper portion (surface) of the channel forming area. Agate electrode of a gate trench structure and a body contact region(n⁺-type semiconductor region) are formed adjacent to the source region.When the p channel trench gate type power MISFET formed in this way isturned off, a gate voltage applied to the gate electrode reaches athreshold voltage or less. In doing so, a channel formed in the sidesurface of the gate electrode is lost to block or interrupt a currentpath, so that no drain current flows. At this time, a back-electromotiveforce occurs in a load having an inductance (L) and is applied to thedrain region of the p channel trench gate type power MISFET.

Thus, a reverse bias voltage is applied to a pn junction formed in theboundary between the p-type semiconductor substrate and the channelforming area (n⁻-type semiconductor region). When the reverse biasvoltage exceeds a junction breakdown voltage of the pn junction,avalanche breakdown due to impact ionization occurs to produce a largeamount of electron positive hole pairs.

On the other hand, the p channel trench gate type power MISFET is formedwith a parasitic pnp bipolar transistor by a source region (p⁺-typesemiconductor region), a channel forming area (n⁻-type semiconductorregion) and a semiconductor substrate (p⁻-type semiconductor region).Positive holes generated upon the occurrence of avalanche breakdown areinjected into the corresponding drain region, and electrons are injectedinto the corresponding body contact region. Here, the channel formingarea corresponds to a base region of the parasitic pnp bipolartransistor. When its base resistance is large, the parasitic pnp bipolartransistor is turned on. That is, when the value of a voltage drop(electron current×rb) developed across the base resistor exceeds about0.7V, an emitter-to-base region is forward-biased so that the parasiticpnp bipolar transistor is turned on. In each cell in which such aparasitic pnp bipolar transistor is turned on, a large currentuncontrollable by the gate electrode of the p channel trench gate typepower MISFET flows, thereby generating heat. Since, at this time, theelectrical resistance of the semiconductor region becomes small due to arise in temperature by the generated heat, the positive feedback that alarger current flows takes place. As a result, the large current flowslocally, thereby causing the breakdown of the p channel trench gate typepower MISFET. This phenomenon is called “avalanche breakdown”. In theautomotive field in particular, there has been a demand for preventingthe avalanche breakdown even though a load having large inductanceexists. The avalanche capability becomes one important property.

In general,-the p channel trench gate type power MISFET has the featurethat it is hard to cause the avalanche breakdown as compared with the nchannel trench gate type power MISFET. This is because the currentamplification gain (hFE) of the pnp bipolar transistor parasiticallyexisting in the p channel trench gate type power MISFET is much smallerthan that of an npn bipolar transistor parasitically existing in the nchannel trench gate type power MISFET. This is also because the mobilityof positive holes corresponding to carriers of the p channel trench gatetype power MISFET is smaller by about ¼ than the mobility of electronscorresponding to carriers of the n channel trench gate type powerMISFET. Accordingly, it can be said that the shortage of avalanchecapability becomes almost insignificant in the single p channel trenchgate type power MISFET.

However, the p channel trench gate type power MISFET with the overheatcutoff circuit built therein presents a problem that the avalanchecapability does not attain to a target value. The reason why theavalanche capability does not attain thereto will be discussed below.

FIG. 6 is a diagram illustrating a circuit for measuring the avalanchecapability of a p channel trench gate type power MISFETI with anoverheat cutoff circuit built therein. FIG. 6 is basically similar inconfiguration to FIG. 4 and is different therefrom in that an overheatcutoff circuit 2 is connected to the p channel trench gate type powerMISFET 1. Switching waveforms at the time that the avalanche capabilityis measured with such a circuit configuration as shown in FIG. 6, areillustrated in FIG. 7. Incidentally, since FIG. 7 is targeted to the pchannel trench gate type power MISFET 1, the vertical axis representsthe plus and minus with being reversed. When a drive voltage is appliedto its corresponding gate pad in FIG. 7, a drain current flows throughthe p channel trench gate type power MISFET 1. At this time, the voltagesimilar to the drive voltage applied to the gate pad is applied even asto the potential of a region VG1 existing between a gate cutoff resistor3 included in the overheat cutoff circuit 2 shown in FIG. 6 and a gateelectrode of the p channel trench gate type power MISFET 1.

Subsequently, when the potential of the gate pad is changed from thedrive voltage to an off voltage, a back-electromotive force due to aninductance (L load) occurs and avalanche breakdown occurs in the pchannel trench gate type power MISFET 1. Therefore, an avalanchebreakdown voltage is applied to a drain pad so that an avalanche peakcurrent (Iap) flows as the drain current. It has been revealed that whenthe gate cutoff resistor 3 does not exist at this time, the potential ofthe region VG1 is also brought to off normally in a manner similar tothe potential of the gate pad, whereas when a large gat cutoff resistor3 exists, the state in which the voltage of a drive voltage level isbeing applied to the region VG1 continues long. Since a large currentflows through the easy-to-turn on p channel trench gate type powerMISFET1 in a concentrated manner while the large voltage remains appliedto the drain pad and source pad in this state, heat is generated so thatthe p channel trench gate type power MISFET1 is destroyed. Thisphenomenon appears pronouncedly as the resistance value of the gatecutoff resistor 3 series-connected to the corresponding gate electrodeof the p channel trench gate type power MISFST1 becomes larger.

This phenomenon is considered to appear for the following reasons. Thatis, it is considered that in the p channel trench gate type powerMISFET1 with the overheat cutoff circuit 2 built therein, the unexpectedlarge gate current flows upon avalanche breakdown based on theinductance (L load), so that a voltage drop is developed across the gatecutoff resistor (5 kΩ to 20 kΩ) 3 series-connected to the gateelectrode. Since the gate electrode is negatively biased at this time,the p channel trench gate type power MISFET1 can lead to a turned-onstate. Since a large current concentratedly flows through each cell lowin on resistance in this state while a large voltage remains appliedbetween the source and drain regions, heat is generated and hence the pchannel trench gate type power MISFET1 is brought to destruction orbreakdown due to thermal runaway beyond an area of safe operation(so-called ASO destruction or breakdown). The phenomenon that the pchannel trench gate type power MISFET1 leads to the ASO breakdown uponthe normal avalanche capability measuring test in this way is adestruction or breakdown phenomenon which does not appear in the singlep channel trench gate type power MISFET1 and is developed only when thelarge gate cutoff resistor 3 peculiar to the overheat cutoff circuit 2exists.

It is now considered that since the overheat cutoff circuit 2 is built,the overheat cutoff circuit 2 may operate when the p channel trench gatetype power MISFET1 generates heat. However, the phenomenon now inquestion is of an avalanche breakdown phenomenon that appears when the pchannel trench gate type power MISFET1 is turned off. That is, it is aproblem at the time that the off voltage is applied to the gateelectrode rather than the drive voltage. The forcible turning-off of thep channel trench gate type power MISFET1 by the overheat cutoff circuit2 will count for nothing.

Thus, it is understood that the problem that the p channel trench gatetype power MISFET1 leads to the ASO breakdown due to the existence ofthe gate cutoff resistor exists. The above-described problem occurs inthe p channel trench gate type power MISFET with the overheat cutoffcircuit built therein, whereas the p channel planar type power MISFETwith the overheat cutoff circuit built therein has high avalanchecapability without causing such a problem. This difference will beexplained.

FIG. 8 is a graph showing relationships between a breakdown voltage(Vdss) between a source region and a drain region and a drain currentdensity (Jds) and between the breakdown voltage (Vdss) and a gatecurrent density (Jg) in a p channel planar type power MISFET. Thehorizontal axis indicates the breakdown voltage (V), and the verticalaxis indicates the drain current density (Jds) and the gate currentdensity (Jg).

It is understood that when the breakdown voltage exceeds −65V as shownin FIG. 8, avalanche breakdown occurs in the p channel planar type powerMISFET, so that a drain current rises sharply. It is however understoodthat a gate current does not increase as shown in FIG. 8 even though theavalanche breakdown occurs in the p channel planar type power MISFET.Thus, since the gate current does not increase in the p channel planartype power MISFET even though the gate cutoff resistor exists, a voltagedrop expressed in the form of the gate cutoff resistor×the gate currentis reduced. Therefore, the phenomenon that the ASO breakdown is reachedis not developed even though the gate cutoff resistor exists.

On the other hand, FIG. 9 is a graph showing relationships between abreakdown voltage (Vdss) between a source region and a drain region anda drain current density (Jds) and between the breakdown voltage (Vdss)and a gate current density (Jg) in a p channel trench gate type powerMISFET. The horizontal axis indicates the breakdown voltage (V), and thevertical axis indicates the drain current density (Jds) and the gatecurrent density (Jg).

It is understood that when the breakdown voltage exceeds −75V as shownin FIG. 9, avalanche breakdown occurs in the p channel trench gate typepower MISFET, so that a drain current rises suddenly. It is understoodthat a gate current also increases remarkably in the p channel trenchgate type power MISFET unlike the p channel planar type power MISFET.This means that carriers (electrons) generated upon the avalanchebreakdown have been injected into the gate electrode. Thus, since thegate current increases in the p channel trench gate type power MISFET, avoltage drop expressed in the form of the gate cutoff resistor×the gatecurrent becomes larger. Since this voltage drop serves in the directionin which a negative bias is applied to the gate electrode, the p channeltrench gate type power MISFET can be brought into a state in which avoltage similar to a drive voltage is applied to its gate electrodedespite the p channel trench gate type power MISFET is being turned off.From this point of view, the phenomenon that since a large currentconcentratedly flows through the easy-to-turn on p channel trench gatetype power MISFET1 while a large voltage remains applied between thesource and drain regions, heat is generated and hence the p channeltrench gate type power MISFET1 is brought to ASO breakdown due tothermal runaway beyond the area of safe operation, becomes manifest.This phenomenon is considered to be a phenomenon that does not appear inthe p channel planar type power MISFET and is peculiar to the p channeltrench gate type power MISFET.

The reason why the gate current is reduced upon the avalanche breakdownin the p channel planar type power MISFET, whereas the gate currentincreases upon the avalanche breakdown in the p channel trench gate typepower MISFET, will next be examined from the viewpoint of theirstructures.

FIG. 10 is a sectional view of a p channel planar type power MISFET. InFIG. 10, the maximum point of electric field at avalanche breakdown isrepresented by each asterisk. As you can see in FIG. 10, it isunderstood that the maximum point of electric field exists in a regionlarge in curvature, of a boundary region (pn junction region) between ap⁻-type epitaxial layer 15 and a channel forming area (n⁻-typesemiconductor region) 16. Impact ionization is easy to occur in themaximum point of electric field, and a large amount of electron positivehole pairs are formed with such impact ionization. The generatedpositive holes flow into the drain region, whereas electrons areinjected into a body contact region (n⁺-type semiconductor region) 17through the channel forming area 16. In the p channel planar type powerMISFET at this time, the distance between the formed position of itsgate electrode and the maximum point of electric field easy to causeimpact ionization is increased, and a generated electron current alsoflows through a position spaced away from the gate electrode. Therefore,very few are capable of injecting the electrons produced upon theavalanche breakdown into the gate electrode, and the phenomenon that theASO breakdown is reached is not developed even though the gate cutoffresistor exists.

On the other hand, FIG. 11 is a sectional view of a p channel trenchgate type power MISFET. Even in FIG. 11, the maximum point of electricfield at avalanche breakdown is represented by each asterisk. As you cansee in FIG. 11, it is understood that the maximum point of electricfield exists in the neighborhood of the bottom of a trench 18 where agate electrode is formed. It is thus understood that the p channeltrench gate type power MISFET takes a structure in which the distancebetween the maximum point of electric field and the gate electrode isvery short. While electron positive hole pairs occur due to impactionization generated in the neighborhood of the maximum point ofelectric field, an electron current flows along each sidewall of thetrench 18 in the p channel trench gate type power MISFET. That is,positive holes flow from a p⁻-type epitaxial layer 15 to a drain region,whereas electrons flow from a channel forming area (n⁻-typesemiconductor region) 16 to a body contact region (n⁺-type semiconductorregion) 17 along the sidewalls of the trench 18 where the gate electrodeis formed. It is understood that paying attention to the path of eachelectron generated upon the avalanche breakdown, the p channel trenchgate type power MISFET takes a structure in which the electronsgenerated upon the avalanche breakdown are easy to be injected into thegate electrode, as compared with the p channel planar type power MISFET.From this point of view, the p channel trench gate type power MISFET hasa high risk of the electrons generated upon the avalanche breakdownbeing injected into the gate electrode. Further, the phenomenon thatsince a large current concentratedly flows in the easy-to-turn on pchannel trench gate type power MISFET1 due to the existence of a gatecutoff resistor while a large voltage remains applied between the sourceand drain regions, heat is generated thereat and the p channel trenchgate type power MISFET1 leads to ASO breakdown due to thermal runawaybeyond the area of safe operation, becomes manifest.

It is understood here that since the electrons are reduced by one digitas compared with the positive holes, the energy necessary to overcomethe potential of a gate insulating film is easy to present a problem atthe p channel trench gate type power MISFET rather than the n channeltrench gate type power MISFET.

All the above are summarized as follows: In the p channel trench gatetype power MISFET with the overheat cutoff circuit built therein, theelectrons generated by the avalanche breakdown at its turning-off areinjected into the gate electrodes. Then, the current based on theinjected electrons flows through the gate cutoff resistor to cause thevoltage drop. With this voltage drop, the p channel trench gate typepower MISFET supposed to be turned off becomes easy to turn on. In doingso, the large current concentratedly flows through the easy-to-turn on pchannel trench gate type power MISFET1 while the large voltage remainsapplied between the source region and the drain region. Therefore, the pchannel trench gate type power MISFET1 generates heat and leads to ASObreakdown due to thermal runaway beyond the area of safe operation.

There is a need to prevent the occurrence of the voltage drop developedacross the gate cutoff resistor for the purpose of solving this problem.It is necessary that since the voltage drop is determined according tothe product of the gate current and the gate cutoff resistor, the gatecurrent or the gate cutoff resistor is reduced as low as possible toreduce the voltage drop.

Firstly, the resistance value of the gate cutoff resistor is consideredlow. Since, however, the oscillation phenomenon that the cut-off orinterruption of the overheat cutoff circuit and its release are repeatedcannot be suppressed when the gate cutoff resistor is lowered, it isdifficult to reduce the gate cutoff resistor.

Thus, secondly, there is considered a method for reducing electronsinjected into the gate electrode upon avalanche breakdown. That is, itis a method for reducing the gate current. If the quantity of electronsinjected into the gate electrode can be reduced by this method, then thep channel trench gate type power MISFET can be prevented from ASObreakdown.

In the p channel trench gate type power MISFET, the electric fieldconcentrates on the bottom of the trench formed with the gate electrodeupon avalanche breakdown. The impact ionization occurs at the bottom ofthe trench on which the electric field concentrates, and the electronpositive hole pairs occur. And the electrons generated due to the impactionization flow into the body contact region by way of each sidewall ofthe trench. It is considered from this result that in order to suppressthe injection of the electrons in the gate electrode upon avalanchebreakdown, the electric field at the bottom of the trench is relaxed andthe current path is formed in other place to reduce the amount ofelectron current flowing through each sidewall of the trench.

The structure of the semiconductor device having realized this methodwill be explained below. FIG. 12 is a plan view typically showing asemiconductor chip 20 formed with the semiconductor device according tothe first embodiment. A power MISFET forming area 21 and an overheatcutoff circuit forming area 22 are formed in the semiconductor chip 20.The p channel trench gate type power MISFET according to the firstembodiment is formed in the power MISFET forming area 21 in s pluralfashion. The respective p channel trench gate type power MISFETs formcells. On the other hand, an overheat cutoff circuit is formed in theoverheat cutoff circuit forming area 22. Described specifically, a gatecutoff resistor and a protective MISFET constituted of a polysiliconfilm are formed therein.

A source pad 23 and a gate pad 24 are formed in the surface of thesemiconductor chip 20. The source pad 23 and the gate pad 24 areexternal connecting terminals. The source pad 23 is connected to asource region of each p channel trench gate type power MISFET. The gatepad 24 is connected to its corresponding gate electrode of the p channeltrench gate type power MISFET. Although not illustrated in FIG. 12, adrain pad is formed in the back surface of the semiconductor chip 20.The drain pad is connected to its corresponding drain region of the pchannel trench gate type power MISFET. Incidentally, no externalconnecting terminals are connected to the overheat cutoff circuit. Thatis, it can be said that the overheat cutoff circuit is built in the pchannel trench gate type power MISFET. It is thus understood that the pchannel trench gate type power MISFET and the overheat cutoff circuitare formed in the same semiconductor chip 20.

Next, FIG. 13 is a sectional view illustrating a sectional structure ofa p channel trench gate type power MISFET. In FIG. 13, a p⁻-typeepitaxial layer 26 is formed over a semiconductor substrate 25comprising p-type monocrystalline silicon. The semiconductor substrate25 and the p⁻-type epitaxial layer 26 result in a drain region of the pchannel trench gate type power MISFET.

A channel forming area 27 constituted of an n⁻-type semiconductor regionis formed over the p⁻-type epitaxial layer 26. A source region 28constituted of a p⁺-type semiconductor region is formed over the channelforming area 27. A trench 29 is formed which extends through the channelforming area 27 from the upper surface of the source region 28 andreaches the interior of the p⁻-type epitaxial layer 26. A gateinsulating film 30 is formed over the inner wall of the trench 29. Agate electrode 31 is formed over the gate insulating film 30 and so asto bury the trench 29. The gate electrode 31 is connected to a gate padthrough a gate cutoff resistor by a lead wiring.

Body contact trenches 32 are formed on the lateral sides of the trench29 buried by the gate electrode 31 with the source region 28 interposedtherebetween. A body contact region (first n-type semiconductor region)33 constituted of an n⁺-type semiconductor region is formed at thebottom of each body contact trench 32. The body contact region 33 isformed in order to reduce base resistance of a parasitic bipolartransistor with the source region 28 as an emitter region, the channelforming area 27 as a base region and the p⁻-type epitaxial layer 26 as acollector region. Incidentally, although the body contact trenches 32are formed and the body contact regions 33 are provided at the bottomsof the body contact trenches 32 in FIG. 13, each body contact region 33may be formed at substantially the same height as the source region 28.That is, although the first embodiment takes such a structure that theposition of the upper surface of the body contact region 33 is placedbelow the bottom of the source region 28 by forming each body contacttrench 32, the body contact region 33 may be formed at substantially thesame height as the source region 28 without forming each body contacttrench 32.

An insulating film 35 is formed over the source regions 28 and the gateelectrode 31. A barrier conductive film 36 is formed over the insulatingfilm 35 and in an area containing the inner walls of the body contacttrenches 32. A wiring 37 is formed over the barrier conductive film 36.The wiring 37 is electrically connected to both of the source regions 28and the body contact regions 33. Thus, the source regions 28 and thebody contact regions 33 are set to the same potential. This is done tosuppress the turning on of the parasitic bipolar transistor by theoccurrence of a potential difference between each source region 28 andits corresponding body contact region 33. This wiring 37 is connected toa source pad formed in the surface of the semiconductor chip.

Next, each n-type semiconductor region (second n-type semiconductorregion) 34 is formed at a portion below the body contact region 33. Onefeature of the present invention is that the n-type semiconductorregions 34 are provided. Each of the n-type semiconductor regions 34 isdisposed in a region deeper than the body contact region 33 andshallower than the bottom of the trench 29. The n-type semiconductorregion 34 is set so as to be higher in impurity concentration than thechannel forming area 27 and lower in impurity concentration than thebody contact region 33.

The impurity concentration of the n-type semiconductor region 34 is sethigher than that of the channel forming area 27 to change an impurityconcentration distribution near the trench 29, thereby making itpossible to reduce the concentration of an electric field on the bottomof the trench 29. As shown in FIG. 14, an avalanche breakdown point canbe shifted to a junction boundary (pn junction) between the n-typesemiconductor region 34 placed at a position spaced away from near thebottom of the trench 29 and the p⁻-type epitaxial layer 26. It is,therefore, possible to suppress the flowing of an electron currentgenerated upon avalanche breakdown through each sidewall of the trench29. As a result, the injection of electrons into the gate electrode 31can be reduced. Accordingly, it is possible to prevent a voltage dropdeveloped across the gate cutoff resistor series-connected to the gateelectrode 31 and to prevent the p channel trench gate type power MISFETsupposed to be turned off from thermal breakdown by its turning-onbeyond the area of safe operation. That is, one feature of the presentinvention is that each n-type semiconductor region 34 higher in impurityconcentration than the channel forming area 27 is disposed between thebody contact region 33 and the bottom of the trench 29 thereby tointentionally cause avalanche breakdown in the area spaced away from theneighborhood of the bottom of the trench 29. Since the avalanchebreakdown is easy to occur as a high-concentration pn junction region isreached, the n-type semiconductor region 34 needs to be set higher inimpurity concentration than the channel forming area 27 from theviewpoint that the avalanche breakdown point is intentionally changed.

On the other hand, when the impurity concentration of the n-typesemiconductor region 34 is high, a breakdown voltage (BVdss) between thesource region 28 and the drain region (p⁻-type epitaxial layer 26) islowered. Therefore, it is not desirable to excessively set high theimpurity concentration from the viewpoint that the breakdown voltage isensured. A problem also arises in that when the impurity concentrationof each n-type semiconductor region 34 is made excessively high, manydefects occur. Thus, in the first embodiment, the impurity concentrationof the n-type semiconductor region 34 is set higher than that of thechannel forming area 27 to change the avalanche breakdown pointintentionally, whereas the impurity concentration thereof is set lowerthan that of the body contact region 33 to ensure the breakdown voltage.

A description will next be made of which position is specifically mostsuitable for the formation of the n-type semiconductor region 34,although each n-type semiconductor region 34 is formed deeper than thebody contact region 33 and formed in the area shallower than the bottomof the trench 29 thereby to change the avalanche breakdown.

FIG. 15 is a graph illustrating a relationship between the rate (depthof n-type semiconductor region 34/depth of channel forming area 27) ofthe depth of the n-type semiconductor region 34 to the depth of thechannel forming area 27 and an avalanche peak current (Iap). Thehorizontal axis expresses the depth of the n-type semiconductor region34 to the depth of the channel forming area 27 in % with the depth ofthe channel forming area 27 as 100%. When, for example, the depth of then-type semiconductor region 34 is shallower than that of the channelforming area 27, the scale of the horizontal axis reaches 100% or less.When the depth of the n-type semiconductor region 34 is deeper than thatof the channel forming area 27, the scale of the horizontal axis reaches100% or more. Here, as is understood through FIG. 13, for example, thedepth of the channel forming area 27 indicates the depth from the uppersurface of the source region 28 to the bottom (boundary between thechannel forming area 27 and the p⁻-type epitaxial layer 26) of thechannel forming area 27 with the upper surface of the source region 28as the reference. Similarly, the depth of the n-type semiconductorregion 34 indicates the depth from the upper surface of the sourceregion 28 to the bottom of the n-type semiconductor region 34. Thevertical axis indicates the avalanche peak current (Iap). An avalanchepeak current at the time that the depth of the n-type semiconductorregion 34 is made identical to that of the channel forming area 27, isassumed to be 100%. An avalanche peak current at the time that the depthof the n-type semiconductor region 34 is changed therefrom, is expressedin relative representation from 100%.

It is understood that as shown in FIG. 15, the avalanche peak currentalso increases as the depth of the n-type semiconductor region 34becomes deeper. That is, it is understood that the more the depth of then-type semiconductor region 34 is formed in the area deeper than thedepth of the channel forming area 27, the more the avalanche capabilitycan be increased.

On the other hand, FIG. 16 is a graph showing a relationship between theratio (depth of n-type semiconductor region 34/depth of channel formingarea 27) of the depth of the n-type semiconductor region 34 to the depthof the channel forming area 27 and a breakdown voltage (BVdss). Thehorizontal axis expresses the depth of the n-type semiconductor region34 to the depth of the channel forming area 27 in % with the depth ofthe channel forming area 27 as 100%. The vertical axis indicates thebreakdown voltage (BVdss) between the source region 28 and the drainregion. A breakdown voltage at the time that the depth of the n-typesemiconductor region 34 is made identical to that of the channel formingarea 27, is assumed to be 100%. A breakdown voltage at the time that thedepth of the n-type semiconductor region 34 is changed therefrom, isexpressed in relative representation from 100%.

It is understood that as shown in FIG. 16, the breakdown voltage isreduced as the depth of the n-type semiconductor region 34 becomesdeeper. That is, it is understood that the more the depth of the n-typesemiconductor region 34 is formed in the area deeper than the depth ofthe channel forming area 27, the more the breakdown voltage is lowered.

From the above description, the deeper the depth of the n-typesemiconductor region 34 than the depth of the channel forming region 27,the more desirable its depth is, from the viewpoint of enhancing theavalanche capability, whereas it is desirable that the depth of then-type semiconductor region 34 is not made deeper than that of thechannel forming area 27 from the viewpoint of no reducing a breakdownvoltage. That is, the avalanche capability and the breakdown voltage areplaced in a relationship of trade-off with respect to the depth of then-type semiconductor region 34. It is thus desirable that from theviewpoint of enhancing the avalanche capability and suppressing areduction in breakdown voltage, the depth of the n-type semiconductorregion 34 is set to be larger than 100% (one times) and smaller than120% (1.2 times). When the depth of the n-type semiconductor region 34is set to 120% with respect to the depth of the channel forming area 27as shown in FIGS. 15 and 16, for example, the avalanche peak current(Iap) can be set to 300% and the breakdown voltage (BVdss) can be set to90%.

The semiconductor device according to the first embodiment isconstituted as mentioned above. The operation thereof will be explainedbelow. The p channel trench gate type power MISFET shown in FIG. 13 isbrought to a state in which the difference in potential is beingproduced between the drain region and the source region 28 formed in thep-type semiconductor substrate 25 (including even p-type epitaxial layer26). Then, a negative voltage is applied to the gate electrode 31 fromthe state in which the gate electrode 31 is grounded and placed in anon-operated state. When the negative voltage is applied to the gateelectrode 31, positive holes existing in the channel forming area 27 arecollected or gathered at the side surface of the trench 29 constitutingthe gate electrode 31, and hence the channel forming area 27 in theneighborhood of the side surface of the trench 29 is inverted to a ptype semiconductor region. The p-type semiconductor region formed bythis inversion results in a channel corresponding to the path of eachpositive hole. The source region and the semiconductor substrate 25(drain region) are coupled to each other by this channel, so that thepositive holes flow between the source region and the drain region.Thus, current flows in the direction of thickness of the semiconductorsubstrate 10 (in the vertical direction) to turn on the p channel trenchgate type power MISFET. Subsequently, when the gate electrode 31 isbrought to a state in which a ground voltage has been applied theretofrom the negative voltage, the channel formed at the side surface of thetrench 29 disappears. Therefore, the source region and the drain regionare electrically disconnected so that the power MISFET is turned off. Byrepeating this sequence of operations, the p channel trench gate typepower MISFET is on/off-operated. Thus, the power MISFET can be used as aswitch by controlling the voltage applied to the gate electrode 31.

The operation of the p channel trench gate type power MISFET at the timethat it is turned off will be described in detail. Assuming that a loadincluding an inductance is connected to the p channel trench gate typepower MISFET, for example, a back-electromotive force occurs in the loadhaving the inductance (L), and the generated back-electromotive force isapplied to the drain region of the p channel trench gate type powerMISFET.

Thus, a reverse bias voltage is applied to a pn junction formed in theboundary between the p⁻-type epitaxial layer 26 and the channel formingarea (n⁻-type semiconductor region). When the reverse bias voltageexceeds a junction breakdown voltage of the pn junction, avalanchebreakdown due to impact ionization occurs to produce a large amount ofelectron positive hole pairs. Since the n-type semiconductor region 34higher in impurity concentration than the channel forming area 27 isformed in the first embodiment, the avalanche breakdown due to theimpact ionization occurs in the neighborhood of the n-type semiconductorregion 34 as shown in FIG. 14. That is, the avalanche breakdown occursin the area spaced away from the bottom of the trench 29.

The positive holes of the electron positive hole pairs generated by theavalanche breakdown flow into the drain region side. On the other hand,the electrons flow from the n-type semiconductor region 34 to the bodycontact region 33 via the channel forming area 27. Since, at this time,the avalanche breakdown point is away from the trench 29, the electroncurrent flows without passing through the neighborhood of each sidewallof the trench 29. Therefore, the injection of the electrons into thegate electrode 31 via the gate insulating film 30 can be reduced.

Thus, since the gate current can be reduced, it is possible to prevent avoltage drop developed across the gate cutoff resistor series-connectedto the gate electrode 31 and prevent the p channel trench gate typepower MISFET supposed to be turned off, from being brought to thermalbreakdown beyond the area of safe operation by its turning-on. Thus,according to the first embodiment, the reliability of the p channeltrench gate type power MISFET with the overheat cutoff circuit builttherein can be enhanced.

The technique executed in the first embodiment to form the highconcentration semiconductor region directly below the body contactregion using the same impurity as the impurity contained in the channelforming area is a technique used even in the improvement of avalanchecapability of a single n channel trench gate type power MISFET. This ishowever completely different from the first embodiment in effect andfunction. This point of view will be explained.

A description will first be made of the single n channel trench gatetype power MISFET. In the single n channel trench gate type powerMISFET, a p-type high-concentration semiconductor region of the sameconduction type as the channel forming area (p type) is formed directlybelow its corresponding body contact region (p type). Thus, the maximumpoint of electric field is designed so as to be directly below the bodycontact region as viewed from the trench bottom, and impact ionizationis caused to occur in this region. As a result, when a pn junctionexisting in the boundary between the channel forming area and the drainregion (n type) is brought to avalanche breakdown, a positive holecurrent generated due to the avalanche breakdown flows from the p-typehigh-concentration semiconductor region to the body contact regionlocated directly thereabove.

It can be said that this shows a state in which the positive holecurrent flows through a resistance-low path in the shortest distance.That is, it can be said that this shows a state in which the baseresistance of a parasitic npn bipolar transistor is set as low aspossible. Therefore, the parasitic npn bipolar transistor is hard toturn on and the n channel trench gate type power MISFET is hard to causeavalanche breakdown. This technique is used in the n channel trench gatetype power MISFET easy to cause the avalanche breakdown.

Consider where this technology is applied to the single p channel trenchgate type power MISFET. Since the p channel trench gate type powerMISFET is hard to cause the avalanche breakdown as compared with the nchannel trench gate type power MISFET, it can be said that the necessityof taking such a structure that an n-type high-concentrationsemiconductor region of the same conduction type as a channel formingarea (n type) is formed directly below its corresponding body contactregion (n type), does not occur so much.

On the other hand, let's consider a p channel trench gate type powerMISFET with an overheat cutoff circuit built therein. In this case, ann-type high-concentration semiconductor region of the same conductiontype as a channel forming area (n type) is formed directly below itscorresponding body contact region (n type). Thus, the maximum point ofelectric field is designed so as to be directly below the body contactregion from the trench bottom, and impact ionization is caused to occurin this region. As a result, when a pn junction existing in the boundarybetween the channel forming area and a drain region (p type) is broughtto avalanche breakdown, an electron current generated due to theavalanche breakdown flows from the n-type high-concentrationsemiconductor region to the body contact region provided directlythereabove.

This acts so as to suppress the flowing of the electron current throughthe neighborhood of each sidewall of the trench and reduce electronsinjected into a gate electrode. Reducing the electrons injected into thegate electrode enables prevention of a voltage drop developed across agate cutoff resistor series-connected to the gate electrode. As aresult, it is possible to suppress the phenomenon that the p channeltrench gate type power MISFET is turned on while a large voltage remainsapplied between the drain and source regions, and to prevent the pchannel trench gate type power MISFET from leading to breakdown ordestruction beyond the area of safe operation.

It is understood that while such a configuration that the p-typehigh-concentration semiconductor region of the same conduction type asthe channel forming area is formed directly below the body contactregion is common between the single n channel trench gate type powerMISFET and the p channel trench gate type power MISFET with the overheatcutoff circuit built therein in this manner, they are respectivelydifferent in effect and function from each other. That is, the single nchannel trench gate type power MISFET is effected for the purpose ofreducing the base resistance of the parasitic npn bipolar transistor,whereas the p channel trench gate type power MISFET with the overheatcutoff circuit built therein is effected for the purpose of preventingthe injection of the electrons into the gate electrode.

Thus, although there is known the technique for forming the p-typehigh-concentration semiconductor region of the same conduction type asthe channel forming area directly below the body contact region in thesingle n channel trench gate type power MISFET, it does not describe theproblem peculiar to the p channel trench gate type power MISFET with theoverheat cutoff circuit built therein, which has been found out by thepresent inventors. In view of this point, the idea itself as to thepoint that a noticeable effect can be attained in that it is possible toavoid the injection of electrons into the gate electrode and therebyprevent the p channel trench gate type power MISFET with the overheatcutoff circuit built therein from leading to breakdown beyond the areaof safe operation, does not exist. This noticeable effect is peculiar tothe p channel trench gate type power MISFET with the overheat cutoffcircuit built therein. It is not considered that this is one at which aperson skilled in the art could have easily arrived from the techniquebased on the single n channel trench gate type power MISFET.

A method for manufacturing the semiconductor device according to thefirst embodiment will next be explained with reference to theaccompanying drawings. FIGS. 17 through 31 are respectively sectionalviews typically showing the process of manufacturing the semiconductordevice. A p channel trench gate type power MISFET forming area, anoverheat cutoff circuit forming area, and a boundary area between the pchannel trench gate type power MISFET and the overheat cutoff circuitforming area are shown in the respective drawings.

As shown in FIG. 17, a semiconductor wafer is first prepared in which ap-type impurity is introduced onto a p-type semiconductor substrate 50to form a p⁻-type epitaxial layer 51. Then, a silicon oxide film (notshown) is formed in the surface (main surface) of the p⁻-type epitaxiallayer 51 by using a thermal oxidation method. Thereafter, a siliconnitride film (not shown) is formed in the entire surface of the p⁻-typeepitaxial layer 51. Next, the silicon nitride film is patterned usingphotolithography technology and etching technology. The patterning isdone in such a manner that the silicon nitride film does not remain inan area in which each device isolation region is formed. Subsequently, aresist film is applied onto the silicon nitride film subjected to thepatterning and thereafter the resist film is patterned usingphotolithography technology. The patterning is done in such a mannerthat well forming regions are made open. For example, phosphorus andarsenic or the like are introduced into the p⁻-type epitaxial layer 51by an ion implantation method with the patterned resist film as a maskto form an n-type well 52. After the impurities have been introduced bythe ion implantation method, heat treatment or annealing is executed toactivate the impurities. The n-type well 52 is formed in the overheatcutoff circuit forming area and the boundary area. Thereafter, theresist film subjected to the patterning is removed. With the patternedsilicon nitride film as a mask, a silicon oxide film is formed by thethermal oxidation method and thereafter the silicon nitride filmsubjected to the patterning is removed, thereby forming each deviceisolation region 53. The device isolation regions 53 are formed in theoverheat cutoff circuit forming area and the boundary area.

Trenches 54 are formed or defined in the p⁻-type epitaxial layer 51 byusing photolithography technology and etching technology as shown inFIG. 18. The trenches 54 are formed in the p channel trench gate typepower MISFET and the boundary area. A gate insulating film 55 is formedover the semiconductor substrate 50 including the bottoms and sidewallsof the trenches 54. The gate insulating film 55 is used as a gateinsulting film of the p channel trench gate type power MISFET.

The gate insulating film 55 is formed of, for example, a silicon oxidefilm. The gate insulating film 55 can be formed using, for example, thethermal oxidation method. However, the gate insulating film 55 is notlimited to the silicon oxide film but can be changed in various ways.The gate insulating film 55 may be formed as a silicon oxynitride film(SiON), for example. That is, such a structure that nitrogen issegregated in the interface between the gate insulting film 55 and thesemiconductor substrate 50 may be taken. The silicon oxynitride filmbrings about high effects to suppress the occurrence of an interfaciallevel in the film and reduce an electron trap as compared with thesilicon oxide film. It is thus possible to enhance hot carrierresistance of the gate insulating film 55 and improve insulationresistance. The silicon oxynitride film is hard to cause the impurity topenetrate therethrough as compared with the silicon oxide film.Therefore, the use of the silicon oxynitride film in the gate insulatingfilm 55 makes it possible to suppress a variation in threshold voltagedue to the diffusion of impurities in a gate electrode into thesemiconductor substrate 50 side. Upon forming the silicon oxynitridefilm, for example, the semiconductor substrate 50 may be heat-treated orannealed in an atmosphere containing nitrogen such as NO, NO₂ or NH₃.Similar effects can be brought about even though after the gateinsulating film 55 constituted of the silicon oxide film is formed inthe surface of the semiconductor substrate 50, the semiconductorsubstrate 50 is heat-treated in an atmosphere containing nitrogen tosegregate nitrogen in the interface between the gate insulating film 55and the semiconductor substrate 50.

The gate insulating film 55 may be formed of, for example, ahigh-permittivity film higher in dielectric constant than the siliconoxide film. The silicon oxide film has heretofore been used as the gateinsulating film 55 from the viewpoint that it is high in insulationresistance and excellent in terms of electrical/physical stability ofsilicon-silicon oxide interface and the like. There has however been ademand for extra-thinning of the thickness of the gate insulating film55 with device micro-fabrication. When the silicon oxide film thin inthis way is used as the gate insulating film 55, a so-called tunnelcurrent occurs in which electrons flowing through a channel of eachMISFET tunnel a barrier formed by the silicon oxide film and flowsthrough the gate electrode.

Therefore, a high-dielectric film has been used which is capable ofincreasing its physical thickness by using a material higher indielectric constant than the silicon oxide film even in the case of thesame capacity. According to the high-dielectric film, a leakage currentcan be reduced because the physical film thickness can be increased eventhough they are made identical in capacity.

For example, a hafnium oxide film (HfO₂ film) corresponding to one ofhafnium oxides is used as the high-dielectric film. However, otherhafnium insulating films such as a hafnium alminate film, HfON film(hafnium oxynitride film), HfSiO film (hafnium silicate film), HfSiONfilm (hafnium silicon oxynitride film) and HfAlO film can be usedinstead of the hafnium oxide film. Further, a hafnium insulating filmobtained by introducing oxides such as tantalum oxide, niobium oxide,titanium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, etc.into theses hafnium insulating films can also be used. Since the hafniuminsulating film is higher in permittivity than the silicon oxide filmand the silicon oxynitride film in a manner similar to the hafnium oxidefilm, effects similar to those obtained where the hafnium oxide film isused can be obtained.

Subsequently, as shown in FIG. 19, a polysilicon film in which a p-typeimpurity (e.g. boron) has been introduced, is formed over thesemiconductor substrate 50 containing the interiors of the trenches 54.The polysilicon film can be formed using, for example, a CVD (ChemicalVapor Deposition) method and is formed so as to bury the interior ofeach trench 54. After the polysilicon film has been formed over thesemiconductor substrate 50 containing the interiors of the trenches 54,a p-type impurity may be introduced into the polysilicon film using theion implantation method.

Next, the polysilicon film is subjected to patterning by usingphotolithography technology and etching technology. With thispatterning, the polysilicon film formed over the semiconductor substrate50 is removed in the p channel trench gate type power MISFET formingarea, and the polysilicon film is left behind only within the trenches54, whereby gate electrodes 56 embedded into the trenches 54 can beformed. A gate lead-out electrode 57 is formed in the boundary area. Thegate lead-out electrode 57 is electrically connected to thecorresponding gate electrode 56.

Subsequently, as shown in FIG. 20, a silicon oxide film 58 is formedover the semiconductor substrate 50 by using the CVD method, forexample. The silicon oxide film 58 is subjected to patterning by usingphotolithography technology and etching technology. The patterning isdone so as to open a channel forming area of each MISFET (includingprotective MISFET) formed in the overheat cutoff circuit forming area.The gate insulating film 55 formed in a layer below the silicon oxidefilm 58 is also removed in the channel forming area. Then, athreshold-voltage (Vth) adjusting impurity is introduced into the openedchannel forming area by using photolithography technology and the ionimplantation method.

Next, as shown in FIG. 21, a gate insulating film 59 is formed over thechannel forming area of the MISFET in the overheat cutoff circuitforming area by using photolithography technology and etchingtechnology. The gate insulting film 59 becomes a gate insulating film ofeach MISFET formed in the overheat cutoff circuit forming area. In amanner similar to the gate insulting film 55 of the p channel trenchgate type power MISFET referred to above, the gate insulating film 59may be formed of the silicon oxide film, silicon oxynitride film orhigh-dielectric film.

Subsequently, a polysilicon film 60 is formed over the semiconductorsubstrate 50. A p-type impurity is introduced into a partial region ofthe polysilicon film 60 by using photolithography technology and the ionimplantation method. The partial region corresponds to a gate electrodeforming area of each MISFET formed in the overheat cutoff circuitforming area. As shown in FIG. 22, the polysilicon film 60 is subjectedto patterning by using photolithography technology and etchingtechnology. Thus, a polysilicon resistive element 61 of 5 kΩ to 20 kΩcan be formed in the boundary area. Gate electrodes 62 can be formed inthe overheat cutoff circuit forming area.

Next, as shown in FIG. 23, an n-type impurity comprised of phosphorus orarsenic or the like is introduced into the p⁻-type epitaxial layer 51 byphotolithography technology and the ion implantation method. Thus, achannel forming area 63 constituted of an n⁻-type semiconductor regionis formed in the p channel trench gate type power MISFET forming area.The channel forming area 63 is formed even in part of the boundary area.Thereafter, it is brought into alignment with each gate electrode 62formed in the overheat cutoff circuit forming area by usingphotolithography technology and the ion implantation method to form ap⁻-type semiconductor region 66. A p-type impurity is introduced byusing the photolithography technology and the ion implantation method.According to this process step, a source region 64 corresponding to ap⁺-type semiconductor region is formed over the channel forming area 63in the p channel trench gate type power MISFET. On the other hand, eachp⁺-type semiconductor region 65 is formed in the polysilicon resistiveelement 61 in the boundary area. Further, p⁺-type semiconductor regions67 and p⁺-type semiconductor regions 68 are formed in the overheatcutoff circuit forming area. The p⁺-type semiconductor region 67 servesas a source region of each MISFET formed in the overheat cutoff circuitforming area. Similarly, the p⁻-type semiconductor region 66 and the p³⁰-type semiconductor region 68 form a drain region of each MISFET formedin the overheat cutoff circuit forming area. Thus, the MISFET formed inthe overheat cutoff circuit forming area takes an offset drain structureso as to be capable of maintaining a high breakdown voltage. That is, ithas a structure in which each p⁻-type semiconductor region 66 is formedbetween the gate electrode 62 and the p⁺-type semiconductor region 68.

Subsequently, as shown in FIG. 24, a silicon oxide film is formed overthe semiconductor substrate 50 and thereafter a silicon nitride film isformed over the silicon oxide film. An insulating film 69 comprising thesilicon oxide film and the silicon nitride film is patterned by usingthe photolithography technology and etching technology. The patterningis done such that the insulating film covers each gate electrode 62.

Next, as shown in FIG. 25, a PSG (Phospho Silicate Glass) film is formedover the semiconductor substrate 50. Thereafter, an SOG (Spin On Glass)film is applied onto the PSG film thereby to form an insulating film 70comprising the PSG film and the SOG film.

Subsequently, a resist film patterned by photolithography technology isformed over the insulating film 70. The patterning is performed in sucha manner that a region for forming each body contact trench is madeopen. The insulating film 70 is etched by etching with the patternedresist film as a mask. After the patterned resist film is removed, thesemiconductor region is etched with the patterned insulating film 70 asa mask thereby to form each body contact trench 71 such as shown in FIG.26.

Thereafter, as shown in FIG. 27, ions are implanted onto the entire mainsurface of the semiconductor substrate 50 thereby to form a body contactregion 72 composed of an n⁺-type semiconductor region at the bottom ofeach body contact trench 71. Since each of the body contact regions 72is formed in the neighborhood of a surface region of the bottom of thebody contact trench 71, the body contact region 72 is formed bylow-energy ion implantation. Thus, even though the ion implantation isdone over the entire main surface of the semiconductor substrate 50, noproblem occurs. That is, the body contact region 72 is formed at thebottom of the body contact trench 71 in a region in which each bodycontact trench 71 is formed, and the ion implantation is cut off orblocked by the insulating film 70 in a region other than the aboveregion.

Next, as shown in FIG. 28, a resist film 73 is formed over theinsulating film 70 by using photolithography technology. The resist film73 is subjected to patterning. The patterning is done in such a mannerthat only the p channel trench gate type power MISFET forming area ismade open. Ion implantation is performed with the patterned resist film73 as a mask. Thus, an n-type semiconductor region 74 is formed in adeep region located directly below each body contact region 72. In the pchannel trench gate type power MISFET forming area, each of the n-typesemiconductor regions 74 is formed in a region deeper than the bodycontact region 72 and shallower than the bottom of the trench in whichthe gate electrode is formed. Further, the impurity concentration of then-type semiconductor region 74 is higher than that of the channelforming area 63 and lower than that of each body contact region 72.Since the n-type semiconductor region 74 is formed in the deep region ofthe bottom of each body contact trench 71, the energy for ionimplantation becomes high energy here. Therefore, there is a possibilitythat when ions are implanted into the entire main surface of thesemiconductor substrate without forming the resist film 73, the ionswill be implanted through the insulating film 70 depending upon thethickness of the insulating film 70 even in a region other than eachbody contact trench 71. Since a device is formed in the verticaldirection in the p channel trench gate type power MISFET forming area,and the impurity concentration of the p-type source region 64 isoverwhelmingly large as compared with the amount of impurity ionsinjected to form each n-type semiconductor region 74, the p channeltrench gate type power MISFET forming area is not subjected to a largeinfluence. However, there is a high possibility that the characteristicof each semiconductor element formed in the overheat cutoff circuitforming area will vary greatly, and it is presumed that an adverseeffect will occur. Thus, in the first embodiment, the resist film 73 isformed and each n-type semiconductor region 74 is formed by ionimplantation with the resist film 73 as a mask. Incidentally, the depthof the n-type semiconductor region 74 is formed to be larger than 100%(one times) and smaller than 120% (1.2 times) with respect to the depthof the channel forming area 63. Thus, while avalanche capability isenhanced, a reduction in breakdown voltage can be suppressed.

When the depths of each trench and channel forming area 63 are fairlydeep, it is necessary to execute ion implantation with higher energy forthe purpose of forming each n-type semiconductor region 74. Since, atthis time, there is a possibility that the ions will be implanted to theposition deeper than the p-type source region 64 thereby to vary thecharacteristic of the p channel trench gate type power MISFET,patterning is preferably carried out as shown in FIG. 29.

Subsequently, after the removal of the resist film 73 as shown in FIG.30, connection holes 75 are formed in the insulating film 70 by usingphotolithography technology and etching technology as shown in FIG. 31.In the boundary area, the connection holes 75 include one that reachesthe gate lead-out electrode 57 and ones that reach the p⁺-typesemiconductor regions 65 of the polysilicon resistive element 61. On theother hand, the connection holes 75 include ones that reach the p⁺-typesemiconductor regions (source regions) 67 and ones that reach thep⁺-type semiconductor regions (drain regions) 68 in the overheat cutoffcircuit forming area.

Next, as shown in FIG. 32, a barrier conductive film (not shown) isformed over the insulating film 70 including each body contact trench 71and each connection hole 75. The barrier conductive film is formed of,for example, a TiW (titanium tungsten) film. The barrier conductive filmcan be formed using a sputtering method, for example. The barrierconductive film has a so-called barrier property that aluminiumcorresponding to a material for an embedding film is prevented frombeing diffused into silicon in a subsequent process step, for example.After the formation of an aluminium film over the barrier conductivefilm, the aluminum film and the barrier conductive film are patterned byusing photolithography technology and etching technology, therebyforming a wiring 76. Although an example formed from the aluminium filmis illustrated as the wiring 76, for example, silicon (Si) and copper(Cu) may be contained in the aluminium film. The gate lead-out electrode57 and the polysilicon resistive element 61 are connected by the wiring76. Therefore, the gate electrode 56 of the p channel trench gate typepower MISFET and the polysilicon resistive element 61 are connected inseries. The polysilicon resistive element 61 is, for example, a gatecutoff resistor in an overheat cutoff circuit.

Subsequently, a protective film (not shown) is formed so as to cover theinsulating film 70 and the wiring 76. Thereafter, predetermined regionson the wiring 76 are made open by photolithography technology andetching technology to form electrode pads. Gate and source pads areformed as the electrode pads. Thus, the corresponding p channel trenchgate type power MISFET with the overheat cutoff circuit built thereincan be formed.

Second Preferred Embodiment

A second embodiment will explain a method of forming body contacttrenches deeper as compared with the first embodiment and forming n-typesemiconductor regions for intentionally changing an avalanche breakdownpoint, in a layer below the body contact trenches.

Process steps from FIGS. 17 to 25 are similar to the first embodiment.Next, as shown in FIG. 33, a resist film subjected to patterning usingphotolithography technology is formed over the insulating film 70. Thepatterning of the resist film is done in such a manner that the regionfor forming each body contact trench is made open. The insulating film70 is etched and patterned with the patterned resist film as a mask.Subsequently, after the removal of the resist film, body contacttrenches 80 that reach the channel forming area 63 are formed with thepatterned insulating film 70 as a mask. The depth of each body contacttrench 80 is formed deeper than that of each body contact trench 71(refer to FIG. 26) formed in the first embodiment.

Subsequently, as shown in FIG. 34, ion implantation is effected on theentire main surface of the semiconductor substrate 50 without using themask based on the resist film thereby to form body contact regions 72each constituted of an n⁺-type semiconductor region at the bottoms ofthe body contact trenches 80. Thereafter, as shown in FIG. 35, ionimplantation is effected on the entire main surface of the semiconductorsubstrate 50 without using the mask based on the resist film thereby toform n-type semiconductor regions 74 directly below the body contactregions 72.

In the first embodiment, the energy for ion implantation was set as highenergy since the n-type semiconductor regions 74 were formed in theregions deeper as viewed from the bottoms of the body contact trenches71 as shown in FIG. 28. Therefore, there is a circumstance that when theions are implanted onto the entire main surface of the semiconductorsubstrate without forming the resist film 73, the ions are injectedthrough the insulating film 70 in the regions other than the bodycontact trenches 71 depending upon the thickness of the insulating film70. In doing so, it is presumed that adverse effects such as a variationin the characteristic of each semiconductor element, etc. will occur.Thus, in the first embodimemt, the resist film 73 was formed and then-type semiconductor region 74 was formed by ion implantation with theresist film 73 as the mask.

On the other hand, in the second embodiment, the depth of each bodycontact trench 80 is formed deeper as shown in FIG. 35. Therefore, then-type semiconductor regions 74 formed directly below the body contactregions 72 can be formed by ion implantation of energy lower than thefirst embodiment. Therefore, in the second embodiment, ions areimplanted on the entire main surface of the semiconductor substrate 50without using the resist film as the mask upon ion implantation forforming each n-type semiconductor region 74. Thus, according to thesecond embodiment, there is an advantage in that since it is unnecessaryto use the mask based on the resist film as in the first embodiment uponforming each n-type semiconductor region 74, a manufacturing process canbe simplified. That is, while the n-type semiconductor region 74 can beformed with the depth of each body contact trench 80, it can be formedwithout using the mask based on the resist film by forming theinsulating film 70 at an ion penetration-free depth. Since no ionspenetrate the insulating film 70, it is possible to prevent adverseeffects such as a variation in characteristic from being exerted on eachsemiconductor element formed in the overheat cutoff circuit formingarea. Incidentally, although there is a case where the body contactregion 72 and the n-type semiconductor region 74 are brought intocontact with each other by bringing the depth of each body contacttrench 80 into deep-grooved form, no problem occurs in electriccharacteristics.

Subsequent process steps are similar to the first embodiment. Even inthe second embodiment as described above, effects similar to the firstembodiment can be obtained.

The advantage of the manufacturing method according to the firstembodiment and the advantage of the manufacturing method according tothe second embodiment will next be explained. The advantage according tothe second embodiment resides in that the n-type semiconductor region 74can be formed without using the mask based on the resist film bybringing each body contact trench 80 into deep-grooved form as describedabove. That is, there is an advantage that the manufacturing process canbe simplified.

There is however a fear that when each body contact trench 80 is broughtinto deep-grooved form, the aspect ratio of the body contact trench 80becomes larger and embeddability is degraded upon formation of thewiring 76 that buries the body contact trench 80. Particularly when acell pith is reduced, this point becomes manifest.

On the other hand, since the mask based on the resist film is used whenthe n-type semiconductor region 74 is formed, it is necessary to add themanufacturing process steps in the first embodiment. Since, however, thebody contact trench 80 is not brought into deep-grooved form, a rise inthe aspect ratio of the body contact trench 80 can be suppressed to aminimum even when the pitch of each cell is miniaturized.

Considering the embeddability of the wiring 76 from the above, themanufacturing method according to the second embodiment is suitablewhere the cell pitch is relatively wide and the aspect ratio of the bodycontact trench 80 does not present a problem so much. On the other hand,when the cell pitch is relatively narrow and the aspect ratio of thebody contact trench 80 presents a problem due to its deep-grooved form,it can be said that the manufacturing method according to the firstembodiment is suitable.

While the invention made above by the present inventors has beendescribed specifically on the basis of the preferred embodiments, thepresent invention is not limited to the embodiments referred to above.It is needless to say that various changes can be made thereto withoutthe scope not departing from the gist thereof.

The present invention can widely be utilized for the manufacturingindustry for manufacturing a semiconductor device.

1. A semiconductor device including a trench gate type MISFET having ap-type channel and a resistive element provided between a gate pad and agate electrode of the trench gate type MISFET, comprising: (a) asemiconductor substrate; (b) a p-type semiconductor region formed overthe semiconductor substrate; (c) an n-type channel forming area formedover the p-type semiconductor region; (d) a p-type source region formedover the n-type channel forming area; (e) a trench which extends from anupper surface of the p-type source region to the p-type semiconductorregion; (f) a gate insulating film formed over an inner wall of thetrench; (g) a gate electrode formed over the gate insulating film andformed so as to bury the trench; (h) a first n-type semiconductor regionformed within the n-type channel forming area and having an impurityintroduced therein in a concentration higher than the n-type channelforming area; and (i) a second n-type semiconductor region formed in aregion deeper than the first n-type semiconductor region and shallowerthan the bottom of the trench, the second n-type semiconductor regionhaving an impurity introduced therein in a concentration lower than thefirst n-type semiconductor region and an impurity introduced therein ina concentration higher than the n-type channel forming area.
 2. Thesemiconductor device according to claim 1, wherein the resistive elementis formed of a polysilicon film.
 3. The semiconductor device accordingto claim 1, wherein the resistance value of the resistive element rangesfrom 5 kΩ to 20 kΩ.
 4. The semiconductor device according to claim 1,wherein the distance from the upper surface of the p-type source regionto the bottom of the second n-type semiconductor region is larger thanone times the distance from the upper surface of the p-type sourceregion to the bottom of the n-type channel forming area and smaller than1.2 times the distance.
 5. The semiconductor device according.to claim1, wherein the positions of an upper surface of the first n-typesemiconductor region is placed below a bottom face of the p-type sourceregion.
 6. The semiconductor device according to claim 5, wherein thefirst n-type semiconductor region and the second n-type semiconductorregion are in contact with each other.
 7. The semiconductor deviceaccording to claim 1, wherein body contact trenches each extending fromthe upper surface of the p-type source region to the n-type channelforming area are formed, and the first n-type semiconductor region isformed at the bottom of each of the body contact trenches.
 8. Thesemiconductor device according to claim 1, wherein an overheat cutoffcircuit is connected to the trench gate type MISFET.
 9. Thesemiconductor device according to claim 8, wherein the resistive elementis used in the overheat cutoff circuit.
 10. The semiconductor deviceaccording to claim 1, wherein the resistive element and the trench gatetype MISFET are connected in series.
 11. A method for manufacturing asemiconductor device including a trench gate type MISFET having a p-typechannel and a resistive element provided between a gate pad and a gateelectrode of the trench gate type MISFET, comprising the steps of: (a)forming a p-type semiconductor region over a semiconductor substrate;(b) forming a trench in the p-type semiconductor region; (c) forming agate insulating film over an inner wall of the trench; (d) forming agate electrode so as to bury the trench; (e) forming an n-type channelforming area in an area shallower than the trench of the p-typesemiconductor region; (f) forming a p-type source region in a surfaceregion shallower than the bottom of the n-type channel forming area; (g)forming a first n-type semiconductor region in the n-type channelforming area; and (h) forming a second n-type semiconductor region in anarea deeper than the first n-type semiconductor region and shallowerthan the bottom of the trench, wherein an impurity concentration of thesecond n-type semiconductor region is lower than that of the firstn-type and higher than that of the n-type channel forming area.
 12. Themethod according to claim 11, wherein the resistance value of theresistive element ranges from 5 kΩ to 20 kΩ.
 13. The method according toclaim 11, wherein the distance from an upper surface of the p-typesource region to the bottom of the second n-type semiconductor region islarger than one times the distance from the upper surface of the p-typesource region to the bottom of the n-type channel forming area andsmaller than 1.2 times the distance.
 14. The method according to claim11, further including the step of: (i) forming body contact trenches inthe n-type channel forming area after the step (f), wherein, in the step(g), the first n-type semiconductor region is formed at the bottom ofeach of the body contact trenches.
 15. The method according to claim 11,further including the step of: (j) forming an interlayer insulating filmover the trenches and the p-type source region before the step (h) afterthe step (f).
 16. The method according to claim 15, further includingthe step of: (k) forming, over the interlayer insulating film, a resistfilm subjected to patterning for creating openings over an area forforming the second n-type semiconductor region after the step (j),wherein, in the step (h), the second n-type semiconductor region isformed by an ion implantation method with the resist film as a maskafter the step (k).
 17. The method according to claim 11, furtherincluding the steps of: (1) forming an interlayer insulting film overthe trenches and the p-type source region after the step (f), and (m)forming body contact trenches reaching the interior of the n-typechannel forming area through the interlayer insulating film, wherein, inthe step (g), the first n-type semiconductor region is formed at thebottom of each of the body contact trenches by ion implantation into theentire main surface of the semiconductor substrate, and wherein, in thestep (h), the second n-type semiconductor region is formed in a regiondeeper than the first n-type semiconductor region by ion implantationinto the entire main surface of the semiconductor substrate, and thedepth of the body contact trench is formed at a depth free ofpenetration of ions through the interlayer insulating film while beingcapable of the second n-type semiconductor region.